dsPIC33CH512MP508 Features
- Operating Conditions:
- 3V to 3.6V, -40°C to +125°C
- Core: Dual 16-Bit dsPIC33CH CPUs
- Master Core 90 MIPS and Slave Core 100 MIPS Operation
- Independent Peripherals for Master Core and Slave Core
- Configurable Shared Resources for Master Core and Slave Core
- Fast 6-Cycle Divide
- Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
- Code Efficient (C and Assembly) Architecture
- 40-Bit Wide Accumulators
- Single-Cycle (MAC/MPY) with Dual Data Fetch
- Single-Cycle, Mixed-Sign MUL Plus 6-Cycle Hardware Divide
- 32-Bit Multiply Support
- Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
- Zero Overhead Looping
- High Performance Peripherals for Real Time Control:
- 4 x 12-bit 3.5 MSPS ADCs: 34 Channels
- High Speed PWMs with 250ps resolution, 12x2 Channels
- Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
- Master Core features:
- Core Frequency 90 MIPS @ 180 MHz
- Program Flash: 512/256 Kbytes Dual Partition with LiveUpdate
- Data RAM: 48/32 Kbytes
- 16-Bit Timer: 1
- DMA: 6
- SCCP (Capture/Compare/Timer): 8
- UART: 2
- SPI/I2S: 2
- I2C: 2
- CAN Flexible Data-Rate (FD): 2 ('50x devices only)
- SENT: 2
- CRC: 1
- QEI: 1
- PTG:1
- CLC: 4
- 16-Bit High-Speed (250ps) PWM: 4x2
- 12-bit, 3.5 Msps ADC: 1, 16 Channels
- Digital Comparator: 4
- 12-Bit DAC/Analog CMP Module: 1
- Watchdog Timer: 1
- Deadman Timer: 1
- Breakpoints: 3 complex, 5 simple
- Oscillator: 1
- Slave Core features:
- Core Frequency 100 MIPS @ 200 MHz
- Program Memory: 72 Kbytes (PRAM) Dual Partition with LiveUpdate
- Data RAM: 16 Kbytes
- 16-Bit Timer: 1
- DMA: 2
- SCCP (Capture/Compare/Timer): 4
- UART: 1
- SPI/I2S: 1
- I2C: 1
- QEI: 1
- CLC: 4
- 16-Bit High-Speed (250ps) PWM: 8x2 Channels
- 12-bit, 3.5 Msps ADC: 3, 18 Channels
- Digital Comparator: 4
- 12-Bit DAC/Analog CMP Module: 3
- Watchdog Timer: 1
- Deadman Timer: 1
- Breakpoints: 1 complex, 2 simple
- Oscillator: 1
- Clock Management:
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Master Reference Clock Output
- Slave Reference Clock Output
- Fail-Safe Clock Monitor (FSCM)
- Fast Wake-up and Start-up
- Backup Internal Oscillator
- LPRC Oscillator
- Power Management:
- Low-Power Management Modes (Sleep, Idle, Doze)
- Integrated Power-on Reset and Brown-out Reset
- Debugger Development Support
- In-Circuit and In-Application Programming
- Simultaneous Debugging Support for Master and Slave Cores
- Master Only Debug and Slave Only Debug Support
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run-Time Watch
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dsPIC33CK64MP105 Features
- Operating Conditions
- 3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MIPS
- dsPIC33CK DSC Core
- Up to 64 KBytes of Program Flash with ECC
- Up to 8 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
- Modified Harvard architecture with 16-bit data and 24-bit instructions
- Code efficient (C and Assembly) CPU architecture designed for real-time applications
- Sixteen 16-bit working registers
- 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
- Single-cycle, mixed-sign 32-bit MUL
- Fast 6-cycle hardware 32/16 and 16/16 DIV
- Dual 40-bit fixed point Accumulators (ACC) for DSP operations
- Single-cycle MAC/MPY with dual data fetch and result write-back
- Zero overhead looping support
- High-Speed PWM Module
- 4 independent PWM pairs (8 total outputs) with up to 250ps resolution
- Dead-time insertion for rising and falling edges and dead-time compensation support
- Clock chopping for high-frequency operation
- Fault and current limit inputs
- Flexible trigger configuration for ADC triggering
- Advanced Analog Features
- 3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
- 12, 16, 19 ADC input channels (depending on package)
- 4 digital comparators for reducing CPU overhead
- 4 oversampling filers up to 256x for increased resolution (up to 16-bits)
- 3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
- Up to 3 op amps with internal connection to ADC Module
- Timer/Counters/Output Compare/Input Capture
- 11 16-bit timer/counters (up to 5 32-bit)
- 4 SCCP
- 1 MCCP
- 10 PWM outputs
- Peripheral Trigger Generator (PTG) for scheduling complex sequences
- 2 Quadrature Encoder Interface (QEI) Modules for optical encoder support
- Communication Interfaces
- 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
- 3 4-wire SPI/I2S up to 40 MHz with dedicated pins
- 2 I2C Modules (up to 1 Mbps) with SMBus support
- 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
- 4 DMA channels supporting UART, SPI, ADC, IC, OC and Timer data transfers
- Special Features
- 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
- Programmable Pin Select (PPS) for peripheral pin function mapping
- On-chip temperature sensor with direct ADC Module connection
- Clock and Power Management
- On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
- Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
- Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
- Low-Power management modes - Sleep, Idle and Doze
- Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)
- Debugger Development Support
- In-Circuit and in application programming and debug support (ICSP)
- On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
- IEEE 1149.2 (JTAG) boundary scan support
- Safety Features
- Dead-Man Timer (DMT) safety feature clocked by instruction fetches
- Watch Dog Timer (WDT)
- CodeGuard™ security for program FLASH
- Programmable Cyclic Redundancy Check (CRC)
- FLASH ECC Fault Injection testing feature
- ICSP™ write inhibit
- Class B Safety Library, IEC 60730
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