Raktárunkba érkezett: PIC32AK6416GC41036-I/M7

Megjelenés dátuma: 2/27/2025

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A PIC32A családból már a PIC32AK6416GC41036 elérhető raktárunkban. Az újonnan bejelentett PIC32A eszközöket a nagy teljesítmény (200 MHz), a felgyorsított matematikai műveletek (dupla pontosságú lebegőpontos egység) és a nagy sebességű, fejlett perifériák jellemzik.

PIC32AK6416GC41036-I/M7 a webáruházban

Jellemzők:

3.0V to 3.6V: -40°C to +85°C, DC to 200 MHz
3.0V to 3.6V: -40°C to +125°C, DC to 200 MHz

32-bit Rich Instruction Set for Optimized Speed and Program Code Size:
Non-paged linear Data/Flash 24-bit addressing space
16-bit/32-bit instructions for optimized code size and performance
32-bit Wide Data Paths
Single and Double Precision Floating-Point Unit (FPU) Coprocessor
Edge or Level Change Notification Interrupt on I/O pins
Peripheral Pin Select (PPS) Remappable Pins to Reduce Board Layout Complexity
Multiple Interrupt Vectors with Individual Programmable Priority
Five External Interrupt Pins
Selectable Oscillator Options Including:
8 MHz, 1% at 0ºC-85ºC Internal Fast RC (FRC) oscillator
8 MHz, 2% Internal Backup Fast RC (BFRC) oscillator with 32 kHz divided output
2 Kbyte Instruction Cache
Sixteen 32-bit Working Registers
Dual 72-bit Accumulators Supporting 32-bit and 16-bit Fixed-Point DSP Operations
Eight Level Deep Working Register Sets
Eight Level Deep Accumulator Register Sets
Eight Level Deep Floating Point Register Sets

Up to 128 Kbytes of Program Flash Memory:
10,000 erase/write cycle endurance
20 years minimum data retention
Self-programmable under software control
Programmable code protection
Flash Error Correcting Code (ECC)
Programmable OTP regions
Entire Flash OTP by ICSP™ write inhibit
64 x128-bit OTP area
High-speed crystal resonator oscillator or external clock
Up to 16 Kbytes of RAM Memory:
6-channel hardware Direct Memory Access (DMA) module
RAM Error Correcting Code (ECC)
RAM Memory Built-In Self-Test (MBIST)

High-Current Sink/Source Capable I/Os
Programmable Weak Pull-Up and Pull-Down Resistors
Programmable Open-Drain Outputs
Two 1.6 GHz PLLs for Peripheral which can be clocked from the FRC or a Crystal Oscillator
Reference Clock Output (REFO)
Low-Power Management Modes (Sleep and Idle)
Power-On Reset and Brown-Out Reset

12-bit Resolution
Up to 40 MSPS Conversion Rate
Up to 22 Analog Input Pins
20 Settings Channels. Each Channel:
Can be assigned to any analog input (I/O pin or internal signal)
Can be set to a different sampling time
Can be configured as single-ended or differential
Conversion result can be formatted as unsigned or signed
Conversion result can be left-aligned (fraction format)
Has a separate 32-bit conversion result register
Supports Four Sampling modes:
Oversampling of multiple samples
Integration of multiple samples
Window (multiple samples accumulated when the gate signal is active)
Single Conversion
All channels have a digital comparator to detect when the conversion result is less than, greater than, in bounds or out of bounds for the configurable thresholds
Last three settings channels have the second result accumulator to implement second order filters
Band Gap Reference and Temperature Sensor Diode Inputs

Three 5 nS Analog Comparators with 12-bit PDM DACs:
Input multiplexing
Slope compensation
One DAC output buffer
Eight Constant-Current Sources

100 V/μS slew rate
1 mV offset (typical)
User calibration of input offset voltage

Three 4-Wire SPI Modules:
32-byte FIFO
Variable data width
I2S mode
Two I2C Modules w/Address Masking and IPMI Support
Three Protocol UARTs with 8-bit RX/TX FIFOs and Automated Handling Support for:
LIN 2.2
DMX
Smart card (ISO 7816)
IrDA®
Two SENT Modules
One Dedicated 32-bit Timer/Counter
Four Single Output Capture/Compare/PWM/Timer (SCCP) Modules:
Flexible configuration as PWM, input capture, output compare or timers
Two 16-bit timers or one 32-bit timer in each module
Single PWM output pin
One Quadrature Encoder Interface (QEI):
Four inputs: Phase A, Phase B, Home, Index
Four Configurable Logic Cells (CLC) with Internal Connections to Select Peripherals and PPS
Serial Encoder Interface BiSS with up to Four Client Encoders Support
Peripheral Trigger Generator (PTG):
10 input trigger sources from other peripheral modules
5 output triggers to other peripheral modules
4 individual interrupt request signals
CPU independent state machine-based instruction sequencer

Immutable Root of Trust (IRT)
Configurable Flash protection regions
Flash access control
Secure Boot
Secure Debug
Device locking

Windowed Watchdog Timer (WDT)
Deadman Timer (DMT)
Four I/O Integrity Monitors (IOIM)
Fail-Safe Clock Monitor (FSCM) with Automatic Switchover to Backup Clock Source with:
Programmable over-frequency/under-frequency thresholds
Flash Error Correcting Code (ECC)
RAM Error Correcting Code (ECC)
RAM Memory Built-In Self-Test (MBIST)
32-bit Cyclic Redundancy Check (CRC) Module
Entire Flash OTP by ICSP™ Write Inhibit
Capless Internal Voltage Regulator
Virtual PPS Pins for Redundancy and Monitoring
Temperature Sensor Diode

Functional Safety

Functional Safety Readiness – ISO 26262/IEC 61508/IEC 60730. To learn about the Functional Safety Readiness of this device family and various Functional Safety standards an application can target using this device family, visit :

Four PWM Generators (Four Pairs, Eight Outputs)
Up to 2.5 ns PWM Resolution
Dead Time for Rising and Falling Edges
Dead-Time Compensation Supports Lower Speed Operation
Fault and Current Limit Inputs
Flexible Trigger Configuration for ADC Triggering

AEC-Q100 REV H:
Grade 1: -40°C to +125°C

Three Programming and Debugging Interfaces:
Two-wire ICSP™ interface with non-intrusive access and real-time data exchange with application
Five Program Addresses and Five Full-Featured Breakpoints
IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan

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